Inputs | Output of NOR Gate | Output of NOT Gate | |
A | B | \[\Upsilon '=\overline{A+B}\] | \[\Upsilon =\overline{\Upsilon }'\] |
0 | 0 | 1 | 0 |
0 | 1 | 0 | 1 |
1 | 0 | 0 | 1 |
1 | 1 | 0 | 1 |
Answer:
As\[\Upsilon =A+B,\] so the new logic gate obtained is an OR gate.
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