A | B | A’ | B’ | \[\Upsilon \] |
0 | 0 | |||
0 | 1 | |||
1 | 0 | |||
1 | 1 |
Answer:
The given set-up is equivalent to an AND gate.
A
B
A’
B’
\[A'+B'\]
\[\Upsilon =\overline{A'+B'}\].
0
0
1
1
1
0
0
1
1
0
1
0
1
0
0
1
1
0
1
1
0
0
0
1
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