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JEE Main & Advanced Physics Semiconducting Devices Question Bank Digital Electronics

  • question_answer
    The logic behind ?NOR? gate is that it gives [CPMT 1999, AFMC 1999]

    A)            High output when both the inputs are low

    B)            Low output when both the inputs are low

    C)            High output when both the inputs are high

    D)            None of these

    Correct Answer: A

    Solution :

                       The Boolean expression for ?NOR? gate is \[Y=\overline{A+B}\]               i.e. if \[A=B=0\](Low), \[Y=\overline{0+0}=\bar{0}=1\](High)


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