| In the following circuit, the output Y for all possible inputs A and B is expressed by the truth table: [AIPMT (S) 2007] |
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A) |
| A B Y |
| 0 0 0 |
| 0 1 0 |
| 1 0 0 |
| 1 1 1 |
B) A B Y 0 0 1 0 0 1 1 0 1 1 1 0
C) A B Y 0 0 1 0 1 0 1 0 0 1 1 0
D) A B Y 0 0 0 0 1 1 1 1 1
Correct Answer: D
Solution :
| Key Idea: Gates-I and II are NOR gates. We can simplify the gate circuit as | |||||||||||||||
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| Here, gates-I and II are NOR gates. The output \[(\overline{A+B})\] of gate-I will be appeared as input of gate-II. The final output is | |||||||||||||||
| \[Y=\overline{\overline{A+B}}\,=A+B\] | |||||||||||||||
| This is he Boolean expression of OR gate whose truth table is given below: | |||||||||||||||
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