To get an output \[Y=1\] from the circuit shown below, the input must be [AIPMT (S) 2010] |
A) A B C 0 1 0
B) 0 0 1
C) 1 0 1
D) 1 0 0
Correct Answer: C
Solution :
Gate I is OR gate \[Y'=\text{ }A+B\] |
Gate II is AND gate \[Y=Y'.\text{ }C\] |
\[\therefore \] \[A=1,B=0,C=1\] will give \[Y=1\] |
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