VIT Engineering VIT Engineering Solved Paper-2014

  • question_answer
    The output Y of the logic circuit shown in figure is best represented as

    A) \[\overset{-}{\mathop{A}}\,++\overline{B.C}\]                

    B)  \[A+\overline{B}.C\]

    C) \[\overline{A+B.C}\]                     

    D)  \[\overline{A+\overset{-}{\mathop{B}}\,.C}\]

    Correct Answer: D

    Solution :

    At logic gate ?I, the Boolean expression is                        \[=1.25\times {{10}^{7}}kWh\] At logic gate-II, the Boolean expression is                        \[i=\frac{5}{20+30}=\frac{5}{50}A\] At logic gate-III, the Boolean expression is                         \[=5\times {{10}^{3}}W\]


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