Answer:
Clearly, the output is low when both the inputs are high otherwise it is high. Hence it is a NAND gate.
When the output of NAND gate is fed to a NOT gate.
Clearly, output \[\Upsilon =A\,.\,B.\] So the new logic gate formed is an AND gate.
Input A
Input B
Output of NAND gate\[\Upsilon '=\overline{\text{A}\text{.B}}\]
Output of NOT gate \[\Upsilon =\overline{\Upsilon }'\]
0
0
1
0
0
1
1
0
1
0
1
0
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